Pepsi Basix Partnership Fund. This patent was filed 18/09/2017 by Epocrates Technology. The patent consists of articles related to the implementation and production of a sealed integrated circuit for each circuit, followed by the reduction of the packaged circuitry and peripheral electronics components via encapsulation measures. Epocrates Technology has a structure for incorporation of semiconductor components in composite form in the package set. Typical example is the package set with electrically insulative insulating layers, encapsulating layers, p-contact layers, and metal traces on the P-type leadframe in its case. Epocrates Technology’s packaging structure includes contacts (spacers), insulating layers (microcrystalline or fine-fine level particles), contact layers (a-type leads, micromachines, or flexible pads for placement of electronic components as external elements) bonded to the contacts, wherein two or more leads are bonded, the leads for the external elements being flat and free from touching or touching the integrated circuits on opposite sides of the traces, and microcrystalline or fine-fine level particles with no internal contact. In addition, typical examples of the epocrates technology include a P-type leads, micromachines, or flexible pad which are bonded to a separate electrode on the chip and associated insulating layers. The electrically insulating layers further include a (4) metal patterning layer which comprises a flexible pad that fills between one micron and tens of nanometers to correspond to dimensions of any component which can be addressed within the package frame depending on cost constraints due to space demands. After packaging the chip, a printed circuit is achieved with one piece of a package set having a photolithographic process. Once the metallization and the assembly of the chip are performed, the package is taken out to a print-on-sandwich mode printing space in which a dielectric layer makes a surface charge detection device with the underlying dielectric.
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The fabrication of the chip-on-sandwich metallization is done by punching out the formed package board in a standard lithography process. The dielectric layer is a ceramic paper made from ceramic or the like. The method of manufacturing chip-on-sandwich is a deposition step using chemical mechanical polishing (CMP) and mechanical polishing processing. In addition, during the metallization to form a printed circuit there are manufacturing and manufacturing techniques that have been developed. In the case of the dielectric layer of the metal patterning material, which has a thickness of less than 5 nm, polishing and metallization processes are used at temperatures 80xc2x0 C., 25xc2x0 C. to 100xc2x0 C., 0.5 to 20xc2x0 C. in the high-temperature-low-not-more-than-80 temperature range to form resist.
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